product description 1 eds-101240 rev e 303 s. technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com the information provided herein is believed to be reliable at press time. sirenza microdevices assumes no responsibility for i naccuracies or omissions. sirenza microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at t he user?s own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. sirenza microdevices doe s not authorize or warrant any sirenza microdevices product for use in life-support devices and/or systems. copyright 2003 sirenza microdevices, inc. all worldwide rights reserved. sirenza microdevices? SHF-0189 is a high performance algaas/gaas heterostructure fet (hfet) housed in a low-cost surface-mount plastic package. the hfet technology improves breakdown voltage while minimiz- ing schottky leakage current resulting in higher pae and improved linearity. output power at 1db compression for the SHF-0189 is +27 dbm when biased for class ab operation at 8v,100ma. the +40 dbm third order intercept makes it ideal for high dynamic range, high intercept point require- ments. it is well suited for use in both analog and digital wireless communi- cation infrastructure and subscriber equipment including 3g, cellular, pcs, fixed wireless, and pager systems. the matte tin finish on sirenza?s lead-free package utilizes a post anneal- ing process to mitigate tin whisker formation and is rohs compliant per eu directive 2002/95. this package is also manufactured with green molding compounds that contain no antimony trioxide nor halogenated fire retar- dants. SHF-0189 SHF-0189z pb rohs compliant & package green 0.05 - 6 ghz, 0.5 watt gaas hfet product features ? now available in lead free, rohs compliant, & green packaging ? high linearity performance at 1.96 ghz +27 dbm p1db +40 dbm output ip3 +16.5 db gain ? high drain efficiency ? see app note an-031 for circuit details applications ? analog and digital wireless systems ? 3g, cellular, pcs ? fixed wireless, pager systems -5 0 5 10 15 20 25 30 35 012345678 typical gain performance (8v,100ma) gain, gmax (db) frequency (ghz) gmax gain sym bol d evice c haracteristics test conditions, 25c v ds =8v, i dq =100m a (unless otherw ise noted) test frequency units min typ max gm ax m axim um available gain z s =z s *, z l =z l * 0.90 ghz 1.96 ghz db - 23.3 20.1 - s 21 ins e rtio n g a in [1 ] z s =z l = 50 ohm s 0.90 ghz 1.96 ghz db 16.6 18.4 14.7 20.2 gain power gain [2 ] a p p lica tio n c ircuit 0.90 ghz 1.96 ghz dbm - 18.6 16.7 - oip3 output third order intercept point [2 ] a p p lica tio n c ircuit 0.90 ghz 1.96 ghz dbm - 40 40 - p1db output 1db c om pression point [2 ] a p p lica tio n c ircuit 0.90 ghz 1.96 ghz dbm - 27.2 27.5 - nf noise figure application c ircuit 1.96 ghz db - 3.2 - i dss s a tura te d d ra in c urre nt v ds = v dsp , v gs = 0v m a 204 294 384 g m tra nco nd ucta nce v ds = v dsp , v gs = -0.25v m s 144 198 252 v p p inch-o ff vo lta g e [1 ] v ds = 2.0v, i ds = 0 .6 m a v -3 .0 -1 .9 -1 .0 bv gs gate-source breakdown voltage [1 ] i gs = 1.2m a, drain open v - -17 -15 bv gd gate-d rain breakdown voltage [1 ] i gd = 1.2m a, v gs = -5.0v v - -22 -17 rth therm al resistance junction-to-lead o c/w - 80 - v ds operating voltage [3 ] drain-source v - - 8.0 i dq operating c urrent [3 ] drain-source, quiescent m a - - 160 p diss p ower d issipation [3 ] w- -0.8 [1] 100% tested - insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] sample tested - samples pulled from each wafer/package lot. sample test specifications are based on statistical data fro m sample test measurements. the test fixture is an engineering application circuit board. the application circuit was designed for the optimum combination of linearity, p1db, and vswr. [3] maximum recommended power dissipation is specified to maintain t j <150c at t l =85c. v ds * i dq <0.8w is recommended for continuous reliable operation.
SHF-0189 0.5 watt hfet 2 eds-101240 rev e 303 s. technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 0.00 0.25 0.50 0.75 1.00 1.25 1.50 -40 -15 10 35 60 85 110 135 160 freq (mhz) v ds (v) i dq (ma) p1db (dbm) oip3* (dbm) gain (db) s11 (db) s22 (db) nf (db) 900 8 100 27.2 40 18.6 -25 -13 4.7 1960 8 100 27.6 40 16.7 -20 -8 3.2 2140 8 100 27.5 40 15.2 -24 -14 3.8 2450 8 100 27.3 40 15.2 -16 -14 3.1 absolute maximum ratings typical performance - engineering application circuits (see app note an-031) data above represents typical performance of the application circuits noted in application note an-031. refer to the application note for additional rf data, pcb layouts, and boms for each application circuit. the application note also includes biasing instructions and other key issues to be considered. for the latest application notes please visit our site at www. sirenza.com or call your local sales representative. * p out = +15dbm per tone, 1mhz tone spacing parameter symbol value unit drain current i ds 200 ma forward gate current i gsf 1.2 ma reverse gate current i gsr 1.2 ma drain-to-source voltage v ds +9.0 v gate-to-source voltage v gs <-5 or >0 v rf input power p in 200 mw operating lead temperature t l see graph c storage temperature range t stor -40 to +150 c power dissipation p diss see graph w channel temperature t j +165 c operation of this device beyond any one of these limits may cause permanent damage. for reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1. mttf is inversely proportional to the device junction temperature. for junction temperature and mttf considerations the bias condition should also satisfy the following expression: p dc < (t j - t l ) / r th where: p dc = i ds * v ds (w) t j = junction temperature (c) t l = lead temperature (pin 4) (c) r th = thermal resistance (c/w) lead temperature (c) total dissipated power (w) power derating curve mttf @ t j =150c exceeds 1e7 hours 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 this area not recommended for continuous reliable operation. operational (tj<150c) abs max (tj<165c)
SHF-0189 0.5 watt hfet 3 eds-101240 rev e 303 s. technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 012345678 de-embedded s-parameters (z s =z l =50 ohms, v ds =8v, i ds =100ma, 25 c) s11 vs frequency s22 vs frequency note: s-parameters are de-embedded to the device leads with z s =z l =50 ? . the data represents typical performace of the device. de-embedded s-parameters can be downloaded from our website (www.sirenza.com). v gs = -2.0 to 0v, 0.2v steps t=25 c dc-iv curves v ds (v) i ds (a) 0.0 0.2 0.5 1.0 2.0 5.0 0.2 0.5 1.0 2.0 5.0 inf 0.2 0.5 1.0 2.0 5.0 1 ghz 4 ghz 8 ghz 6 ghz 3 ghz 2 ghz s22 0.0 0.2 0.5 1.0 2.0 5.0 0.2 0.5 1.0 2.0 5.0 inf 0.2 0.5 1.0 2.0 5.0 1 ghz 4 ghz 8 ghz 6 ghz 3 ghz 2 ghz s11 -5 0 5 10 15 20 25 30 35 012345678 -50 -45 -40 -35 -30 -25 -20 -15 -10 frequency (ghz) gain, gmax (db) isolation (db) gain & isolation isolation gain gmax
SHF-0189 0.5 watt hfet 4 eds-101240 rev e 303 s. technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com caution: esd sensitive appropriate precautions in handling, packaging and testing devices must be observed. part number ordering information the part will be symbolized with the ?h1? designator and a dot signifying pin 1 on the top surface of the package. part symbolization pin # function description 1 gate rf input 2 source connection to ground. use via holes to reduce lead inductance. place vias as close to ground leads as possible. 3drainrf output 4 source same as pin 2 pin description mounting and thermal considerations it is very important that adequate heat sinking be provided to minimize the device junction temperature. the following items should be implemented to maximize mttf and rf performance. 1. multiple solder-filled vias are required directly below the ground tab (pin 4). [critical] 2. incorporate a large ground pad area with multiple plated- through vias around pin 4 of the device. [critical] 3. use two point board seating to lower the thermal resistance between the pcb and mounting plate. place machine screws as close to the ground tab (pin 4) as possible. [recommended] 4. use 2 ounce copper to improve the pcb?s heat spreading capability. [recommended] recommended mounting configuration for optimum rf and thermal performance shf-0x89 machine screws plated thru holes (0.020" dia) ground plane .016 .118 .019 .096 .041 .177 .068 .059 .015 .161 4 3 2 1 dimensions are in inches package dimensions h1z 1 2 3 123 4 h1 1 2 3 123 4 part number reel size devices/reel SHF-0189 7" 1000 SHF-0189z 7" 1000
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